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? semiconductor components industries, llc, 1999 october, 1999 rev. 2 1 publication order number: mc34071/d "
" !# quality bipolar fabrication with innovative design concepts are employed for the mc33071/72/74, mc34071/72/74 series of monolithic operational amplifiers. this series of operational amplifiers offer 4.5 mhz of gain bandwidth product, 13 v/ m s slew rate and fast setting time without the use of jfet device technology. although this series can be operated from split supplies, it is particularly suited for single supply operation, since the common mode input voltage range includes ground potential (v ee ). with a darlington input stage, this series exhibits high input resistance, low input offset voltage and high gain. the all npn output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink ac frequency response. the mc33071/72/74, mc34071/72/74 series of devices are available in standard or prime performance (a suffix) grades and are specified over the commercial, industrial/vehicular or military temperature ranges. the complete series of single, dual and quad operational amplifiers are available in plastic dip, soic and tssop surface mount packages. ? wide bandwidth: 4.5 mhz ? high slew rate: 13 v/ m s ? fast settling time: 1.1 m s to 0.1% ? wide single supply operation: 3.0 v to 44 v ? wide input common mode voltage range: includes ground (v ee) ? low input offset voltage: 3.0 mv maximum (a suffix) ? large output voltage swing: 14.7 v to +14 v (with 15 v supplies) ? large capacitance drive capability: 0 pf to 10,000 pf ? low total harmonic distortion: 0.02% ? excellent phase margin: 60 ? excellent gain margin: 12 db ? output short circuit protection ? esd diodes/clamps provide input protection for dual and quad p suffix case 626 http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information pin connections (single, top view) (dual, top view) offset null v ee nc v cc output offset null inputs v ee inputs 1 inputs 2 output 2 output 1 v cc 1 2 3 4 8 7 6 5 + + 1 2 3 4 8 7 6 5 + 1 8 1 8 so8 d suffix case 751 inputs 1 output 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 (quad, top view) 4 2 3 1 pin connections 1 2 3 4 5 6 78 9 10 11 12 13 14 + + + + 14 1 14 1 14 1 p suffix case 646 so14 d suffix case 751a tssop14 dtb suffix case 948g
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 2 offset null (mc33071, mc34071 only) q1 q2 q3 q4 q5 q6 q7 q17 q18 d2 c2 d3 r6 r7 r8 r5 q15 q16 q14 q13 q11 q10 r2 c1 r1 q9 q8 q12 d1 r3 r4 inputs v cc output current limit v ee /gnd base current cancellation + q19 bias representative schematic diagram (each amplifier) maximum ratings rating symbol value unit supply voltage (from v ee to v cc ) v s +44 v input differential voltage range v idr note 1 v input voltage range v ir note 1 v output short circuit duration (note 2) t sc indefinite sec operating junction temperature t j +150 c storage temperature range t stg 60 to +150 c notes: 1. either or both input voltages should not exceed the magnitude of v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded (see figure 1).
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 3 electrical characteristics (v cc = +15 v, v ee = 15 v, r l = connected to ground, unless otherwise noted. see note 3 for t a = t low to t high ) a suffix nonsuffix characteristics symbol min typ max min typ max unit input offset voltage (r s = 100 w , v cm = 0 v, v o = 0 v) v cc = +15 v, v ee = 15 v, t a = +25 c v cc = +5.0 v, v ee = 0 v, t a = +25 c v cc = +15 v, v ee = 15 v, t a = t low to t high v io e e e 0.5 0.5 e 3.0 3.0 5.0 e e e 1.0 1.5 e 5.0 5.0 7.0 mv average temperature coefficient of input offset voltage r s = 10 w , v cm = 0 v, v o = 0 v, t a = t low to t high d v io / d t e 10 e e 10 e m v/ c input bias current (v cm = 0 v, v o = 0 v) t a = +25 c t a = t low to t high i ib e e 100 e 500 700 e e 100 e 500 700 na input offset current (v cm = 0 v, v o = 0v) t a = +25 c t a = t low to t high i io e e 6.0 e 50 300 e e 6.0 e 75 300 na input common mode voltage range t a = +25 c t a = t low to t high v icr v ee to (v cc 1.8) v ee to (v cc 2.2) v ee to (v cc 1.8) v ee to (v cc 2.2) v large signal voltage gain (v o = 10 v, r l = 2.0 k w ) t a = +25 c t a = t low to t high a vol 50 25 100 e e e 25 20 100 e e e v/mv output voltage swing (v id = 1.0 v) v cc = +5.0 v, v ee = 0 v, r l = 2.0 k w , t a = +25 c v cc = +15 v, v ee = 15 v, r l = 10 k w , t a = +25 c v cc = +15 v, v ee = 15 v, r l = 2.0 k w , t a = t low to t high v oh 3.7 13.6 13.4 4.0 14 e e e e 3.7 13.6 13.4 4.0 14 e e e e v v cc = +5.0 v, v ee = 0 v, r l = 2.0 k w , t a = +25 c v cc = +15 v , v ee = 15 v, r l = 10 k w , t a = +25 c v cc = +15 v, v ee = 15 v, r l = 2.0 k w , t a = t low to t high v ol e e e 0.1 14.7 e 0.3 14.3 13.5 e e e 0.1 14.7 e 0.3 14.3 13.5 v output short circuit current (v id = 1.0 v, v o = 0 v, t a = 25 c) source sink i sc 10 20 30 30 e e 10 20 30 30 e e ma common mode rejection r s 10 k w , v cm = v icr , t a = 25 c cmr 80 97 e 70 97 e db power supply rejection (r s = 100 w ) v cc /v ee = +16.5 v/16.5 v to +13.5 v/13.5 v, t a = 25 c psr 80 97 e 70 97 e db power supply current (per amplifier, no load) v cc = +5.0 v, v ee = 0 v, v o = +2.5 v, t a = +25 c v cc = +15 v, v ee = 15 v, v o = 0 v, t a = +25 c v cc = +15 v, v ee = 15 v, v o = 0 v, t a = t low to t high i d e e e 1.6 1.9 e 2.0 2.5 2.8 e e e 1.6 1.9 e 2.0 2.5 2.8 ma notes: 3. t low = 40 c for mc33071, 2, 4, /a t high = +85 c for mc33071, 2, 4, /a =0 c for mc34071, 2, 4, /a = +70 c for mc34071, 2, 4, /a
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, r l = connected to ground. t a = +25 c, unless otherwise noted.) a suffix nonsuffix characteristics symbol min typ max min typ max unit slew rate (v in = 10 v to +10 v, r l = 2.0 k w , c l = 500 pf) a v = +1.0 a v = 1.0 sr 8.0 e 10 13 e e 8.0 e 10 13 e e v/ m s setting time (10 v step, a v = 1.0) to 0.1% (+1/2 lsb of 9bits) to 0.01% (+1/2 lsb of 12bits) t s e e 1.1 2.2 e e e e 1.1 2.2 e e m s gain bandwidth product (f = 100 khz) gbw 3.5 4.5 e 3.5 4.5 e mhz power bandwidth a v = +1.0, r l = 2.0 k w , v o = 20 v pp , thd = 5.0% bw e 160 e e 160 e khz phase margin r l = 2.0 k w r l = 2.0 k w , c l = 300 pf f m e e 60 40 e e e e 60 40 e e deg gain margin r l = 2.0 k w r l = 2.0 k w , c l = 300 pf a m e e 12 4.0 e e e e 12 4.0 e e db equivalent input noise voltage r s = 100 w , f = 1.0 khz e n e 32 e e 32 e nv/ h z equivalent input noise current f = 1.0 khz i n e 0.22 e e 0.22 e pa/ h z differential input resistance v cm = 0 v r in e 150 e e 150 e m w differential input capacitance v cm = 0 v c in e 2.5 e e 2.5 e pf total harmonic distortion a v = +10, r l = 2.0 k w , 2.0 v pp v o 20 v pp , f = 10 khz thd e 0.02 e e 0.02 e % channel separation (f = 10 khz) e e 120 e e 120 e db open loop output impedance (f = 1.0 mhz) |z o | e 30 e e 30 e w figure 1. power supply configurations figure 2. offset null circuit single supply split supplies 1 2 3 4 v cc v ee v cc v cc v ee v ee 1 2 3 4 3.0 v to 44 v v cc +|v ee | 44 v offset nulling range is approximately 80 mv with a 10 k potentiometer (mc33071, mc34071 only). v cc v ee 1 2 3 4 5 6 7 10 k +
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 5 r l connected to ground t a = 25 c r l = 10 k r l = 2.0 k v o , output voltage swing (v pp ) figure 3. maximum power dissipation versus temperature for package types figure 4. input offset voltage versus temperature for representative units figure 5. input common mode voltage range versus temperature figure 6. normalized input bias current versus temperature figure 7. normalized input bias current versus input common mode voltage figure 8. split supply output voltage swing versus supply voltage t a , ambient temperature ( c) d p , maximum power dissipation (mw) 55 40 20 0 20 40 60 80 100 120 140 160 8 & 14 pin plastic pkg so14 pkg so8 pkg t a , ambient temperature ( c) io v , input offset voltage (mv) 55 25 0 25 50 75 100 12 5 v cc = +15 v v ee = 15 v v cm = 0 t a , ambient temperature ( c) icr v , input common mode voltage range (v) 55 25 0 25 50 75 100 125 v cc v cc /v ee = +1.5 v/ 1.5 v to +22 v/ 22 v v ee t a , ambient temperature ( c) ib i , input bias current (normalized) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v v cm = 0 v ic , input common mode voltage (v) 12 8.0 4.0 0 4.0 8.0 12 v cc = +15 v v ee = 15 v t a = 25 c v cc , |v ee |, supply voltage (v) 0 5.0 10 15 20 25 v ib i , input bias current (normalized) 2400 2000 1600 1200 800 400 0 4.0 2.0 0 2.0 4.0 v cc v cc 0.8 v cc 1.6 v cc 2.4 v ee +0.01 v ee 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.4 1.2 1.0 0.8 0.6 50 40 30 20 10 0
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 6 v cc v cc = +15 v r l to v cc t a = 25 c gnd v cc v cc = +15 v r l = gnd t a = 25 c gnd v o , output voltage swing (v pp ) figure 9. single supply output saturation versus load resistance to v cc 60 figure 10. split supply output saturation versus load current figure 11. single supply output saturation versus load resistance to ground figure 12. output short circuit current versus temperature figure 13. output impedance versus frequency figure 14. output voltage swing versus frequency 0 5.0 10 15 20 i l, load current ( ma) v cc v ee sink v cc /v ee = +5.0 v/ 5.0 v to +22 v/ 22 v t a = 25 c source r l , load resistance to ground ( w ) 100 1.0 k 10 k 100 k sat v , output saturation voltage (v) r l , load resistance to v cc ( w ) 100 1.0 k 10 k 100 k t a , ambient temperature ( c) sc i , output current (ma) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v r l 0.1 w d v in = 1.0 v sink source f, frequency (hz) o z , output impedance ( ) w 1.0 k 10 k 100 1.0 m 10 m a v = 1000 a v = 100 a v = 10 a v = 1.0 v cc = +15 v v ee = 15 v v cm = 0 v o = 0 d i o = 0.5 ma t a = 25 c f, frequency (hz) 3.0 k 10 k 30 k 100 k 300 k 1.0 m 3.0 m v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k thd 1.0% t a = 25 c sat v , output saturation voltage (v) sat v , output saturation voltage (v) v cc v cc 1.0 v cc 2.0 v ee +2.0 v ee +1.0 v ee v cc 2.0 v cc 4.0 v cc 0.2 0.1 0 0 0.4 0.8 2.0 1.0 50 40 30 20 10 0 50 40 30 20 10 0 28 24 20 16 12 8.0 4.0 0
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 7 1. phase r l = 2.0 k 2. phase r l = 2.0 k, c l = 300 pf 3. gain r l = 2.0 k 4. gain r l = 2.0 k, c l = 300 pf v cc = +15 v v ee = 15 v v o = 0 v t a = 25 c phase margin = 60 gain margin = 12 db 3 4 1 2 gain v cc = +15 v v ee = 15 v v o = 0 v r l = 2.0 k t a = 25 c phase phase margin = 60 figure 15. total harmonic distortion versus frequency figure 16. total harmonic distortion versus output voltage swing figure 17. open loop voltage gain versus temperature figure 18. open loop voltage gain and phase versus frequency figure 19. open loop voltage gain and phase versus frequency figure 20. normalized gain bandwidth product versus temperature f, frequency (hz) 10 100 1.0 k 10 k 100 k a v = 1000 a v = 100 a v = 10 a v = 1.0 v cc = +15 v v ee = 15 v v o = 2.0 v pp r l = 2.0 k t a = 25 c v o , output voltage swing (v pp ) thd, total harmonic distortion (%) 0 4.0 8.0 12 16 20 v cc = +15 v v ee = 15 v r l = 2.0 k t a = 25 c a v = 1000 a v = 100 a v = 10 a v = 1.0 t a , ambient temperature ( c) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v v o = 10 v to +10 v r l = 10 k f 10hz f, frequency (hz) 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m 100 m , excess phase (degrees) f , excess phase (degrees) f f, frequency (mhz) 1.0 2.0 3.0 5.0 7.0 10 20 30 t a , ambient temperature ( c) gbw, gain bandwidth product (normalied) 55 25 0 25 50 75 100 12 5 v cc = +15 v v ee = 15 v r l = 2.0 k vol a, o p e n loo p v ol t age gai n ( d b) 0.4 0.3 0.2 0.1 0 4.0 3.0 2.0 1.0 0 116 112 108 104 100 96 100 80 60 40 20 0 20 10 0 10 20 30 40 1.15 1.1 1.05 1.0 0.95 0.9 0.85 0 45 90 135 180 100 120 140 160 180 thd , t o t al h ar m o n ic d is t or t io n ( % ) vol a, o p e n loo p v ol t age gai n ( d b) vol a , open loop voltage gain (db)
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 8 v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k to v o = 10 v to +10 v t a = 25 c figure 21. percent overshoot versus load capacitance figure 22. phase margin versus load capacitance figure 23. gain margin versus load capacitance figure 24. phase margin versus temperature figure 25. gain margin versus temperature figure 26. phase margin and gain margin versus differential source resistance percent overshoot c l , load capacitance (pf) 10 100 1.0 k 10 k v cc = +15 v v ee = 15 v r l = 2.0 k v o = 10 v to +10 v t a = 25 c c l , load capacitance (pf) , phase margin (degrees) f m 10 100 1.0 k 10 k v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k to v o = 10 v to +10 v t a = 25 c c l , load capacitance (pf) m a , gain margin (db) 10 100 1.0 k 10 k , phase margin (degrees) f m t a , ambient temperature ( c) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k to v o = 10 v to +10 v c l = 10 pf c l = 100 pf c l = 1,000 pf c l = 10,000 pf t a , ambient temperature ( c) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k to v o = 10 v to +10 v c l = 10 pf c l = 1,000 pf m a , gain margin (db) c l = 100 pf c l = 10,000 pf phase m a , gain margin (db) r t , differential source resistance ( w ) 1.0 100 1.0 k 10 k 10 100 k r 1 r 2 v o + v cc = +15 v v ee = 15 v r t = r 1 + r 2 a v = +100 v o = 0 v t a = 25 c gain , phase margin (degrees) f m 100 80 60 40 20 0 70 60 50 40 30 20 10 0 14 12 10 8.0 6.0 2.0 0 4.0 80 60 40 20 0 16 12 8.0 4.0 0 12 10 8.0 6.0 4.0 2.0 0 60 50 40 30 20 10 0 70
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 9 figure 27. normalized slew rate versus temperature figure 28. output settling time figure 29. small signal transient response figure 30. large signal transient reponse figure 31. common mode rejection versus frequency figure 32. power supply rejection versus frequency t a , ambient temperature ( c) sr, sle w ra t e ( n or m ali z e d ) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k c l = 500 pf t s , settling time ( m s) o v , output voltage swing from 0 v (v) d 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = +15 v v ee = 15 v a v = 1.0 t a = 25 c 10 mv 1.0 mv 1.0 mv compensated uncompensated 10 mv 1.0 mv 1.0 mv 50 mv/div 2.0 m s/div v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k c l = 300 pf t a = 25 c 5.0 v/div 1.0 m s/div f, frequency (hz) c m r, co mm o n m o d e re j ec t io n ( d b) 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m t a = 25 c t a = 125 c t a = 55 c v cc = +15 v v ee = 15 v v cm = 0 v d v cm = 1.5 v f, frequency (hz) psr, power supply rejection (db) 0.1 1.0 10 100 1.0 k 10 k 100 k 1.0 m 10 m v cc = +15 v v ee = 15 v t a = 25 c ( d v cc = +1.5 v) ( d v ee = +1.5 v) +psr psr v cc = +15 v v ee = 15 v a v = +1.0 r l = 2.0 k c l = 300 pf t a = 25 c 1.15 1.1 1.05 1.0 0.95 0.9 0.85 10 5.0 0 5.0 10 0 0 100 80 60 40 20 0 100 80 60 40 20 0 d v cm d v o a dm cmr = 20 log d v cm d v o x a dm + d v o a dm + d v cc d v ee d v o /a dm d v cc +psr = 20 log d v o /a dm d v ee psr = 20 log
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 10 figure 33. supply current versus supply voltage figure 34. power supply rejection versus temperature figure 35. channel separation versus frequency figure 36. input noise versus frequency v cc , |v ee |, supply voltage (v) cc i , supply current (ma) 0 5.0 10 15 20 25 t a = 25 c t a = 125 c t a = 55 c t a , ambient temperature ( c) psr, power supply rejection (db) 55 25 0 25 50 75 100 125 v cc = +15 v v ee = 15 v ( d v cc = +1.5 v) ( d v ee = +1.5 v) +psr psr f, frequency (khz) channel separation (db) 10 20 30 50 70 100 200 300 v cc = +15 v v ee = 15 v t a = 25 c f, frequency (khz) n e , input noice voltage ( i , input noise current (pa ) 10 100 1.0 k 10 k 100 k nv hz ) hz n voltage current 9.0 8.0 7.0 6.0 5.0 4.0 105 95 85 75 65 120 100 80 60 40 20 0 70 60 50 40 30 20 10 0 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 d v o a dm + d v cc d v ee d v o /a dm d v cc +psr = 20 log d v o /a dm d v ee psr = 20 log v cc = +15 v v ee = 15 v v cm = 0 t a = 25 c applications information circuit description/performance features although the bandwidth, slew rate, and settling time of the mc34071 amplifier series are similar to op amp products utilizing jfet input devices, these amplifiers offer other additional distinct advantages as a result of the pnp transistor differential input stage and an all npn transistor output stage. since the input common mode voltage range of this input stage includes the v ee potential, single supply operation is feasible to as low as 3.0 v with the common mode input voltage at ground potential. the input stage also allows differential input voltages up to 44 v, provided the maximum input voltage range is not exceeded. specifically, the input voltages must range between v ee and v cc supply voltages as shown by the maximum rating table. in practice, although not recommended, the input voltages can exceed the v cc voltage by approximately 3.0 v and decrease below the v ee voltage by 0.3 v without causing product damage, although output phase reversal may occur. it is also possible to source up to approximately 5.0 ma of current from v ee through either inputs clamping diode without damage or latching, although phase reversal may again occur. if one or both inputs exceed the upper common mode voltage limit, the amplifier output is readily predictable and may be in a low or high state depending on the existing input bias conditions. since the input capacitance associated with the small geometry input device is substantially lower (2.5 pf) than the typical jfet input gate capacitance (5.0 pf), better frequency response for a given input source resistance can be achieved using the mc34071 series of amplifiers. this performance feature becomes evident, for example, in fast settling dtoa current to voltage conversion applications where the feedback resistance can form an input pole with the input capacitance of the op amp. this input pole creates a 2nd order system with the single pole op amp and is therefore detrimental to its settling time. in this context, lower input capacitance is desirable especially for higher
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 11 values of feedback resistances (lower current dacs). this input pole can be compensated for by creating a feedback zero with a capacitance across the feedback resistance, if necessary, to reduce overshoot. for 2.0 k w of feedback resistance, the mc34071 series can settle to within 1/2 lsb of 8 bits in 1.0 m s, and within 1/2 lsb of 12bits in 2.2 m s for a 10 v step. in a inverting unity gain fast settling configuration, the symmetrical slew rate is 13 v/ m s. in the classic noninverting unity gain configuration, the output positive slew rate is +10 v/ m s, and the corresponding negative slew rate will exceed the positive slew rate as a function of the fall time of the input waveform. since the bipolar input device matching characteristics are superior to that of jfets, a low untrimmed maximum offset voltage of 3.0 mv prime and 5.0 mv downgrade can be economically offered with high frequency performance characteristics. this combination is ideal for low cost precision, high speed quad op amp applications. the all npn output stage, shown in its basic form on the equivalent circuit schematic, offers unique advantages over the more conventional npn/pnp transistor class ab output stage. a 10 k w load resistance can swing within 1.0 v of the positive rail (v cc ), and within 0.3 v of the negative rail (v ee ), providing a 28.7 v pp swing from 15 v supplies. this large output swing becomes most noticeable at lower supply voltages. the positive swing is limited by the saturation voltage of the current source transistor q 7 , and v be of the npn pull up transistor q 17 , and the voltage drop associated with the short circuit resistance, r 7 . the negative swing is limited by the saturation voltage of the pulldown transistor q 16 , the voltage drop i l r 6 , and the voltage drop associated with resistance r 7 , where i l is the sink load current. for small valued sink currents, the above voltage drops are negligible, allowing the negative swing voltage to approach within millivolts of v ee . for large valued sink currents (>5.0 ma), diode d3 clamps the voltage across r 6 , thus limiting the negative swing to the saturation voltage of q 16 , plus the forward diode drop of d3 ( v ee +1.0 v). thus for a given supply voltage, unprecedented peaktopeak output voltage swing is possible as indicated by the output swing specifications. if the load resistance is referenced to v cc instead of ground for single supply applications, the maximum possible output swing can be achieved for a given supply voltage. for light load currents, the load resistance will pull the output to v cc during the positive swing and the output will pull the load resistance near ground during the negative swing. the load resistance value should be much less than that of the feedback resistance to maximize pull up capability. because the pnp output emitterfollower transistor has been eliminated, the mc34071 series offers a 20 ma minimum current sink capability, typically to an output voltage of (v ee +1.8 v). in single supply applications the output can directly source or sink base current from a common emitter npn transistor for fast high current switching applications. in addition, the all npn transistor output stage is inherently fast, contributing to the bipolar amplifier's high gain bandwidth product and fast settling capability. the associated high frequency low output impedance (30 w typ @ 1.0 mhz) allows capacitive drive capability from 0 pf to 10,000 pf without oscillation in the unity closed loop gain configuration. the 60 phase margin and 12 db gain margin as well as the general gain and phase characteristics are virtually independent of the source/sink output swing conditions. this allows easier system phase compensation, since output swing will not be a phase consideration. the high frequency characteristics of the mc34071 series also allow excellent high frequency active filter capability, especially for low voltage single supply applications. although the single supply specifications is defined at 5.0 v, these amplifiers are functional to 3.0 v @ 25 c although slight changes in parametrics such as bandwidth, slew rate, and dc gain may occur. if power to this integrated circuit is applied in reverse polarity or if the ic is installed backwards in a socket, large unlimited current surges will occur through the device that may result in device destruction. special static precautions are not necessary for these bipolar amplifiers since there are no mos transistors on the die. as with most high frequency amplifiers, proper lead dress, component placement, and pc board layout should be exercised for optimum frequency performance. for example, long unshielded input or output leads may result in unwanted inputoutput coupling. in order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. this not only minimizes the input pole for optimum frequency response, but also minimizes extraneous apick upo at this node. supply decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. the output of any one amplifier is current limited and thus protected from a direct short to ground. however, under such conditions, it is important not to allow the device to exceed the maximum junction temperature rating. typically for 15 v supplies, any one output can be shorted continuously to ground without exceeding the maximum temperature rating.
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 12 figure 37. ac coupled noninverting amplifer figure 38. ac coupled inverting amplifier (typical single supply applications v cc = 5.0 v) figure 39. dc coupled inverting amplifer maximum output swing figure 40. unity gain buffer ttl driver figure 41. active highq notch filter figure 42. active bandpass filter + v cc 5.1 m 20 k c in v in 1.0 m mc34071 v o 0 3.7 v pp r l 10 k a v = 101 100 k 1.0 k bw (3.0 db) = 45 khz c o v o 36.6 mv pp + 3.7 v pp 0 v cc v o 100 k c in 10 k 100 k c o r l 10 k 68 k v in 370 mv pp a v = 10 bw (3.0 db) = 450 khz + 4.75 v pp v o v o v cc r l 100 k 91 k 5.1 k 1.0 m a v = 10 v in 2.63 v 5.1 k bw (3.0 db) = 450 khz + v in 2.5 v 0 0 to 10,000 pf cable ttl gate + v in v o 16 k c 0.01 32 k 2.0 r 2.0 c 0.02 f o = 1.0 khz f o = v in 0.2 vdc 1 4 p rc 2.0 c 0.02 16 k r r + v in v o v cc r3 2.2 k c 0.047 r2 5.6 k 0.4 v cc r1 f o = 30 khz h o = 10 h o = 1.0 1.1 k given f o = center frequency a o = gain at center frequency choose value f o , q, a o , c r3 = r1 = r2 = q r3 r1 r3 2h o 4q 2 r1r3 p f o c for less than 10% error from operational amplifier q o f o gbw < 0.1 where f o and gbw are expressed in hz. c 0.047 mc34071 mc34071 mc34071 mc34071 mc34071 mc54/74xx then: gbw = 4.5 mhz typ.
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 13 figure 43. low voltage fast d/a converter figure 44. high speed low voltage comparator figure 45. led driver figure 46. transistor driver figure 47. ac/dc ground current monitor figure 48. photovoltaic cell amplifier 5.0 k 10 k bit switches c f r f v o v cc (r2r) ladder network settling time 1.0 m s (8bits, 1/2 lsb) + 5.0 k 5.0 k 10 k 10 k + v o v o v in 1.0 v 2.0 k r l 2.0 v 4.0 v 0.1 t 25 v/ m s 0.2 m s delay delay 1.0 m s v in t 13 v/ m s + v cc v ref aono v in < v ref aono v in > v ref v in + v cc v cc r l r l (a) pnp (b) npn + + v o i load r1 r2 r s ground current sense resistor v o = i load r s bw ( 3.0 db) = gbw for v o > 0.1v r1 r2 r1+r2 r2 + v o mc34071 i cell v cell = 0 v v o = i cell r f v o > 0.1 v r f 1+ mc34071 mc34071 mc34071 mc34071 mc34071 mc34071
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 14 figure 49. low input voltage comparator with hysteresis figure 50. high compliance voltage to sink current converter figure 51. high input impedance differential amplifier figure 52. bridge current amplifier figure 53. low voltage peak detector figure 54. high frequency pulse width modulation v ref r2 v o v oh v ol v inl v inh v ref hysteresis v in v in r1 mc34071 v inl =(v ol v ref )+v ref r1 r1+r2 v inh =(v oh v ref )+v ref v h =(v oh v ol ) + r1 r1+r r1 r1+r2 v in i out r + i out = v in v io r 1/2 mc34072 + + r1 r2 r3 r4 v o +v1 +v2 r2 r4 r3 r1 (critical to cmrr) v o = 1 v2v1 for (v2 v1), v > 0 = + r4 r3 r4 r3 + +v ref r f v o rr r r = d r d r < < r r f > > r (v o 0.1 v) r f v o = v ref d r r f 2r 2 + v in v in r l v p 10,000 pf v o = v in (pk) + v p t + + v p t t i out v p + 0 + i sc base charge removal i b v+ 47 k 100 k c r pulse width control group osc comparator high current output f osc v 0.85 rc 100 k i b mc34071 mc34071 mc34071 1/2 mc34072 1/2 mc34072 1/2 mc34072
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 15 figure 55. second order lowpass active filter figure 56. second order highpass active filter general additional applications information v s = 15.0 v figure 57. fast settling inverter figure 58. basic inverting amplifier figure 59. basic noninverting amplifier figure 60. unity gain buffer (a v = +1.0) + r1 r3 560 510 c2 c1 0.44 0.02 r2 5.6 k mc34071 f o = 1.0 khz h o = 10 choose: f o , h o , c2 then: c1 = 2c2 (h o +1) r2 = r3 = r1 = r2 h o h o +1 4 p f o c2 r2 + c2 0.05 c1 1.0 r1 46.1 k r2 1.1 k f o = 100 hz h o = 20 choose: f o , h o , c1 then: r1 = r2 = c2 = h o +0.5 p f o c1 2 p f o c1 (1/h o +2) c h o c1 1.0 + c f * v o = 10 v step r f 2.0 k i high speed dac *optional compensation uncompensated compensated t s = 1.0 m s to 1/2 lsb (8bits) t s = 2.2 m s to 1/2 lsb (12bits) sr = 13 v/ m s v o + r1 r2 v o v in r l bw (3.0 db) = gbw = sr = 13 v/ m s v o v in r2 r1 r1 +r2 r1 bw (3.0 db) = gbw r1 +r2 r1 + v in v o r2 r l r1 = v o v in r2 r1 1 + + v in v o bw p = 200 khz v o = 20 v pp sr = 10 v/ m s mc34071 mc34071 mc34071 mc34071 mc34071 2 2 2
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 16 figure 61. high impedance differential amplifier figure 62. dual voltage doubler r r e example: let: r = r e = 12 k then: a v = 3.0 bw = 1.5 mhz a v = 1 + 2 r r e + + + v o r r r r r mc34074 + + 100 k 10 +10 10 220 pf v o +v o r l +v o v o 18.93 18.78 10 k 18 18 5.0 k 15.4 15.4 r l 100 k 100 k r l + + + + + 10 10 10 mc34074 mc34074 mc34074 mc34074 mc34074
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 17 ordering information op amp function device operating temperature range package shipping single mc34071p, mc34071ap mc34071d, mc34071ad mc34071dr2, mc34071adr2 t a = 0 to +70 c dip8 so8 so8 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel mc33071p, mc33071ap mc33071d, mc33071ad mc33071dr2, mc33071adr2 t a = 40 to +85 c dip8 so8 so8 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel dual mc34072p, mc34072ap mc34072d, mc34072ad mc34072dr2, mc34072adr2 t a = 0 to +70 c dip8 so8 so8 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel mc33072p, mc33072ap mc33072d, mc33072ad mc33072dr2, mc33072adr2 t a = 40 to +85 c dip8 so8 so8 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel mc34072vd mc34072vdr2 t a = 40 to +125 c so8 so8 / tape & reel 98 units / rail 2500 units / tape & reel quad mc34074p, mc34074ap mc34074d, mc34074ad mc34074dr2, mc34074adr2 t a = 0 to +70 c dip8 so8 so8 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel MC33074p, MC33074ap MC33074d, MC33074ad MC33074dr2, MC33074adr2 MC33074dtb, MC33074adtb MC33074dtbr2, MC33074adtbr2 t a = 40 to +85 c dip8 so8 so8 / tape & reel tssop14 tssop14 / tape & reel 50 units / rail 98 units / rail 2500 units / tape & reel 96 units / rail 2500 units / tape & reel mc34074vd mc34074vdr2 t a = 40 to +125 c so8 so8 / tape & reel 98 units / rail 2500 units / tape & reel
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 18 package dimensions p suffix plastic package case 62605 issue k d suffix (so8) plastic package case 75105 issue r notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m 10 10 n 0.76 1.01 0.030 0.040 seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.18 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeters. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 19 package dimensions p suffix plastic package case 64606 issue l d suffix (so14) plastic package case 751a03 issue f notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc34071,2,4,a mc33071,2,4,a http://onsemi.com 20 package dimensions dtb suffix (tssop14) plastic package case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane w. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ?? ?? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n usa/europe literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line *: 3036752167 8003443810 toll free usa/canada *to receive a fax of our publications n. america technical support : 8002829855 toll free usa/canada on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent r ights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1418549 phone : 81354878345 email : r14153@onsemi.com on semiconductor website: http://onsemi.com for additional information, please contact your local sales representative. mc34071/d

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